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Topic summary

Posted by kath
 - Dec 28, 2009, 09:18 AM
Quote from: Cognitive on Sep 15, 2008, 10:38 AM
VLSI Project Titles

1.   Energy efficient novel architectures for the lifting-based discrete wavelet transform. September 2007

2.   Pipelined Array-Based FIR Filter Folding

3.   Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. March 2007

4.   Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Jan. 2007

5.   Application Dependent Testing for FPGA. March 2007

6.   FPGA-based fault emulation of synchronous sequential circuits

7.   FPGA based Space Vector PWM Control IC for Three Phase Induction Motor Drive

8.   FPGA Implementation of Parallel Pipelined Multiplier less FFT Architecture. Oct. 2007

9.   FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.

10.   A Spatial Median Filter for Noise Removal in Digital Images. April 2008

11.   Hardware Implementation of 1D Wavelet Transform on an FPGA for Infrasound Signal Classification. Feb. 2008
Posted by Kalyan
 - Sep 15, 2008, 10:38 AM
VLSI Project Titles

1.   Energy efficient novel architectures for the lifting-based discrete wavelet transform. September 2007

2.   Pipelined Array-Based FIR Filter Folding

3.   Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. March 2007

4.   Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. Jan. 2007

5.   Application Dependent Testing for FPGA. March 2007

6.   FPGA-based fault emulation of synchronous sequential circuits

7.   FPGA based Space Vector PWM Control IC for Three Phase Induction Motor Drive

8.   FPGA Implementation of Parallel Pipelined Multiplier less FFT Architecture. Oct. 2007

9.   FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.

10.   A Spatial Median Filter for Noise Removal in Digital Images. April 2008

11.   Hardware Implementation of 1D Wavelet Transform on an FPGA for Infrasound Signal Classification. Feb. 2008