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CPU DESIGN_3

Started by ganeshbala, Apr 18, 2008, 06:42 PM

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ganeshbala

Apr 18, 2008, 06:42 PM Last Edit: Apr 18, 2008, 06:46 PM by ganeshbala
The control sequence for execution of these two ADD instructions are different. Of course, the fetch phase of all the instructions remain same.

It is clear that control signals depend on the instruction, i.e., the contents of the instruction register. It is also observed that execution of some of the instructions depend on the contents of condition code or status flag register, where the control sequence depends in conditional branch instruction.
Hence, the required control signals are uniquely determined by the following information:
Contents of the control counter.

Contents of the instruction register.

Contents of the condition code and other status flags.
The external inputs represent the state of the CPU and various control lines connected to it, such as MFC status signal. The condition codes/ status flags indicates the state of the CPU. These includes the status flags like carry, overflow, zero, etc.

Programmable Logic Array


In this discussion, we have presented a simplified view of the way in which the sequence of control signals needed to fetch and execute instructions may be generated.
It is observed from the discussion that as the number of instruction increases the number of required control signals will also increase.
In VLSI technology, structure that involve regular interconnection patterns are much easier to implement than the random connections.
One such regular structure is PLA ( programmable logic array ). PLAs are nothing but the arrays of AND gates followed by array of OR gates. If the control signals are expressed as sum of product form then with the help of PLA it can be implemented.

Microprogrammed Control

In hardwired control, we saw how all the control signals required inside the CPU can be generated using a state counter and a PLA circuit.
There is an alternative approach by which the control signals required inside the CPU can be generated . This alternative approach is known as microprogrammed control unit.
In microprogrammed control unit, the logic of the control unit is specified by a microprogram.
A microprogram consists of a sequence of instructions in a microprogramming language. These are instructions that specify microoperations.
A microprogrammed control unit is a relatively simple logic circuit that is capable of (1) sequencing through microinstructions and (2) generating control signals to execute each microinstruction.
The concept of microprogram is similar to computer program. In computer program the complete instructions of the program is stored in main memory and during execution it fetches the instructions from main memory one after another. The sequence of instruction fetch is controlled by program counter (PC) .
Microprogram are stored in microprogram memory and the execution is controlled by microprogram counter ( PC).
Microprogram consists of microinstructions which are nothing but the strings of 0's and 1's. In a particular instance, we read the contents of one location of microprogram memory, which is nothing but a microinstruction. Each output line ( data line ) of microprogram memory corresponds to one control signal. If the contents of the memory cell is 0, it indicates that the signal is not generated and if the contents of memory cell is 1, it indicates to generate that control signal at that instant of time.
First let me define the different terminologies that are related to microprogrammed control unit.

Control Word (CW) :

Control word is defined as a word whose individual bits represent the various control signal. Therefore each of the control steps in the control sequence of an instruction defines a unique combination of 0s and 1s in the CW.
A sequence of control words (CWs) corresponding to the control sequence of a machine instruction constitutes the microprogram for that instruction.
The individual control words in this microprogram are referred to as microinstructions.
The microprograms corresponding to the instruction set of a computer are stored ina aspecial memory which will be referred to as the microprogram memory. The control words related to an instructions are stored in microprogram memory.
Each microinstruction basically provides the required control signal at that time step. The microprogram counter ensures that the control signal will be delivered to the various parts of the CPU in correct sequence.
We have some instructions whose execution depends on the status of condition codes and status flag, as for example, the branch instruction. During branch instruction execution, it is required to take the decision between the alternative action.
To handle such type of instructions with microprogrammed control, the design of control unit is based on the concept of conditional branching in the microprogram. For that it is required to include some conditional branch microinstructions.
In conditional microinstructions, it is required to specify the address of the microprogram memory to which the control must direct. It is known as branch address. Apart from branch address, these microinstructions can specify which of the states flags, condition codes, or possibly, bits of the instruction register should be checked as a condition for branching to take place.
Let us examine the contents of microprogram memory and how the microprogram of each instruction is stored or organized in microprogram memory. Consider the two example that are used in our previous lecture . First example is the control sequence for execution of the instruction "Add contents of memory location addressed in memory direct mode to register R1".
Steps Actions
1. PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2. Zout, PCin, Wait For MFC
3. MDRout, IRin
4. Address-field-of-IRout, MARin, Read
5. R1out, Yin, Wait for MFC
6. MDRout, Add, Zin
7. Zout, R1in
8. END
Control sequence for Conditional Branch instruction (BRN) Branch on negative)
Steps Actions
1. PCout, MARin, Read, Clear Y, Set Carry-in to ALU, Add , Zin
2. Zout, PCin, Wait for MFC
3. MDRout, IRin
4. PCout, Yin
5. Address field-of IRout, Add, Zin
6. Zout, PCin
7. End
First consider the control signal required for fetch instruction , which is same for all the instruction, we are listing them in a particular order.
PCout MARin Read Clear Y Set Carry to ALU Add Zin Zout PCin WMFC MDRout IRin
The control word for the first three steps of the above two instruction are : ( which are the fetch cycle of each instruction as follows ):
Step1 1 1 1 1 1 1 1 0 0 0 0 0 - - -
Step2 0 0 0 0 0 0 0 1 1 1 0 0 - - -
Step3 0 0 0 0 0 0 0 0 0 0 1 1 - - -
We are storing this three CW in memory location 0, 1 and 2. Each instruction starts from memory location 0. After executing upto third step, i.e., the contents of microprogram memory location 2, this control word stores the instruction in IR. The starting address generator circuit now calculate the starting address of the microprogram for the instruction which is available in IR.
Consider that the microprogram for add instruction is stored from memory location 50 of microprogram memory. So the partial contents from memory location 50 are as follows :
Location 50 0 1 1 0 0 0 0 0 0 0 0 0 - - - - - -
51 0 0 0 0 0 0 0 0 0 1 0 0 - - - - - -
and so on . . . .

The contents of the compile instruction is given below:
1 - PCin, 2 - PCout, 3 - MARin, 4 - Read, 5 - MDRout, 6 - IRin, 7 - , 8 - Yin, 9 - Clear Y,
10 - Carry-in, 11 - add, 12 - Zin, 13 - Zout, 14 -RIout, 15 - RIin, 16 - WMFC, 17 - END.
Memory Location --------- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 ---------- 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 -----------
1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 ----------
2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 ---------
|
|
50 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0
51 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0
52 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0
53 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


When the microprogram executes the End microinstruction of an instruction, then it generates the End control signal. This End control signal is used to load the PC with the starting address of fetch instruction ( In our case it is address 0 of microprogram memory). Now the CPU is ready to fetch the next instruction from main memory.
From the discussion, it is clear that microprograms are similar to computer program, but it is in one level lower, that's why it is called microprogram.
For each instruction of the instruction set of the CPU, we will have a microprogram.
While executing a computer program, we fetch instruction by instruction from main memory which is controlled by program counter(PC).
When we fetch an instruction from main memory, to execute that instruction , we execute the microprogram for that instruction. Microprograms are nothing but the collection of microinstrctions. These microinstructions will be fetched from microprogram memory one after another and its sequence is maintained by PC. Fetching of microinstruction basically provides the required control signal at that time instant.
In the previous discussion, to design a micro programmed control unit, we have to do the following:
For each instruction of the CPU, we have to write a microprogram to generate the control signal. The microprograms are stored in microprogram memory (control store). The starting address of each microprogram are known to the designer
Each microprogram is the sequence of microintructions. And these microinstructions are executed in sequence. The execution sequence is maintained by microprogram counter.
Each microinstructions are nothing but the combination of 0's and 1's which is known as control word. Each position of control word specifies a particular control signal. 0 on the control word means that a low signal value is generated for that control signal at that particular instant of time, similarly 1 indicates a high signal.
Since each machine instruction is executed by a corresponding micro routine, it follows that a starting address for the micro routine must be specified as a function of the contents of the instruction register (IR).
To incorporate the branching instruction, i.e., the branching within the microprogram, a branch address generator unit must be included. Both unconditional and conditional branching can be achieved with the help of microprogram. To incorporate the conditional branching instruction, it is required to check the contents of condition code and status flag.
Microprogramed controlled control unit is very much similar to CPU. In CPU the PC is used to fetch instruction from the main memory, but in case of control unit, microprogram counter is used to fetch the instruction from control store.
But there are some differences between these two. In case of fetching instruction from main memory, we are using two signals MFC and WMFC. These two signals are required to synchronize the speed between CPU and main memory. In general, main memory is a slower device than the CPU.
In microprogrammed control the need for such signal is less obvious. The size of control store is less than the size of main memory. It is possible to replace the control store by a faster memory, where the speed of the CPU and control store is almost same.
Since control store are usually relatively small, so that it is feasible to speed up their speed through costly circuits.
If we can implement the main memory by a faster device then it is also possible to eliminate the signals MFC & WMFC. But, in general, the size of main memory is very big and it is not economically feasible to replace the whole main memory by a faster memory to eliminate MFC & WMFC.
Grouping of control signals:
It is observed that we need to store the information of each control signal in control store. The status of a particular control signal is either high or low at a particular instant of time.
It is possible to reserve one bit position for each control signal. If there are n control signals in a CPU, them the length of each control signal is n . Since we have one bit for each control signal, so a large number of resources can be controlled with a single microinstruction. This organization of microinstruction is known as horizontal organization.
If the machine structure allows parallel uses of a number of resources, then horizontal organization has got advantage. Since more number of resources can be accessed parallel, the operating speed is also more in such organization. In this situation, horizontal organization of control store has got advantage.
If more number of resources can be accessed simultaneously, than most of the contents of control store is 0. Since the machine architecture does not provide the parallel access of resources, so simultaneously we cannot generate the control signal. In such situation, we can combine some control signals and group them together. This will reduce the size of control word. If we use compact code to specify only a small number of control functions in each microinstruction, then it is known as vertical organization of microinstruction.
In case of horizontal organization, the size of control word is longer, which is in one extreme point and in case of vertical organization, the size of control word is smaller, which is in other extreme.
In case of horizontal organization, the implementation is simple, but in case of vertical organization, implementation complexity increases due to the required decoder circuits. Also the complexity of decoder depends on the level of grouping and encoding of the control signal.
Horizontal and Vertical organization represent the two organizational extremes in microprogrammed control. Many intermediate schemes are also possible, where the degree of encoding is a design parameter.
We will explain the grouping of control signal with the help of an example. Grouping of control signals depends on the internal organization of CPU.
Assigning individual bits to each control signal is certain to lead to long microinstruction, since the number of required control signals is normally large.
However, only a few bits are set to 1 and therefore used for active gating in any given microinstructions. This obviously results in low utilization of the available bit space.
If we group the control signal in some non-over lapping group then the size of control word reduces

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